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TEL : +81-3-4212-2575
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National Institute of Informatics
Room: 1604

PUBLICATIONS

Most important publications (Top 10)
Refereed publications, published books
Patents
Awards

Papers on Network-on-Chip are available from Prof. Matsutani's page

Correction(10/12/2017)The wrong grant number was described in the Acknowledgement. We have corrected it as the paper. Y.Hu,H.Hara,I.Fujiwara,H.Matsutani,H.Amano,M.Koibuchi, ``Towards Tightly-coupled Datacenter with Free-space Optical Links,'' Int. Conf. on Cloud and Big Data Computing(ICCBDC) 2017 (to appear).

Most important publications ( Top 10 )

1 HPCA Ikki Fujiwara, Michihiro Koibuchi, Tomoya Ozaki, Hiroki Matsutani, Henri Casanov a, Augmenting Low-latency HPC Network with Free-space Optical Links, The 21st IEEE International Symposium on High Performance Computer Architecture (HPCA 2015), pp.390-401, Feb 2015 paper, slides
Our FSO HPC is introduced in IEEE Spectrum, June 2015, "Giving supercomputers a second wind", Boyd, J., June 2015, p.20
1 HPCA Michihiro Koibuchi, Ikki Fujiwara, Hiroki Matsutani, Henri Casanova, Layout-conscious Random Topologies for HPC Off-chip Interconnects, The 19th International Symposium on High-Performance Computer Architecture (HPCA), Feb. 2013, paper, slides
TPDS Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova, Swap-and-randomize: A Method for Building Low-latency HPC Interconnects IEEE Transactions on Parallel and Distributed Systems (to be published),
1 ISCA Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casano va, ``A Case for Random Shortcut Topologies for HPC Interconnects'', The 39th International Symposium on Computer Architecture (ISCA), pp.177-188, June 2012 paper, slides
1 IEEE TPDS Michihiro Koibuchi, Tomohiro Otsuka, Tomohiro Kudoh, Hideharu Amano, ``A Switch-tagged Routing Methodology for PC Clu sters with VLAN Ethernet'', IEEE Transactions on Parallel and Distributed System s, Vol.22, No.2, pp.217-230, Feb 2011
2 HPCA Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, and Tsutomu Yos hinaga, ``Prediction Router: Yet Another Low Latency On-Chip Router Architecture '',The 15th International Symposium on High-Performance Computer Architecture, p p.367-378, Feb 2009 paper, slides
IEEE TC Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yosh inaga, "Prediction Router: A Low-Latency On-Chip Router Architecture with Multip le Predictors", IEEE Transactions on Computers (TC), Vol.60, No.6, pp.783-799, J un 2011,
3 HPCA Daichi Fujiki, Kiyo Ishii, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Henri Casanova, Michihiro Koibuchi, ``High-Bandwidth Low-Latency Approximate Interconnection Networks'',The International Symposium on High-Performance Computer Architecture, Feb 2017 (to appear)
4 IEEE TVLSI Takahiro Kagami,Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda,Hideharu Amano,``Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces'', IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (to appear)
5 TCADHiroki Matsutani, Michihiro Koibuchi, Dais uke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano, ``Performance, Area, and Power Evaluations of Ultra Fine-Grained Run-Time Power-Gating Routers for CMPs'', IEEE Transactions on Computer-Aided Design of Integrated Circuits (T CAD), Vol.30, No.4, pp.520-533. Apr 2011
6 DAC M. Koibuchi, L. Leong. T.Totoki, N.Niwa, H. Matsutani, H. Amano, H. Casanova, Sparse 3-D NoCs with Inductive Coupling, Th e 56th Design Automation Conference (DAC), 6 pages Jun 2019
8 IEEE TPDS J. Flich, T. Skeie, A.Mejia, O. Lysne, P. Lopez, A. Robles, J. Duato, M. Koibuch i, T. Rokicki, and J. C. Sancho, ``A Survey and Evaluation of Topology Agnostic Routing Algorithms'', IEEE Transactions on Parallel and Distributed Systems, Vol .23, No.3, pp.405-425, Mar. 2012

Page Top

Recent Selected Papers


  1. On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconne ct Bottleneck Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano,Tadao Nakamura, Proc. of the ACM/IEEE International Symposium on Networks-on-Chip (NOCS), 2015 ( to appear)
  2. Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova Skywalk: a Topology for HPC Networks with Low-delay Switches The 28th IEEE International Parallel & Distributed Processing Symposium (IPDPS), p p.263-272, May 2014 paper, slides
  3. Yasuhiro Take, Hiroki Matsutani, Daisuke Sasaki, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano, ``3-D NoC with Inductive-Coupling Links for Building-Block SiPs'', IEEE Transactions on Computers (TC), vol.63, issue 3, pp.748-763, 2014, DOI:10.1109/TC.2012.249
  4. Hiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu, Hideharu Amano, ``Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips'', Proc. of the 17th Design, Automation, and Test in Europe Conference (DATE'14), pp.1-6, Mar 2014.
  5. Van K. Nguyen, Nhat T. X. Le, Ikki Fujiwara, Michihiro Koibuchi, Distributed Shortcut Networks: Layout-aware Low-degree Topologies Exploiting Small -world Effect, the International Conference on Parallel Processing(ICPP), pp.572-581, Oct 2013

Refereed publications, published books

  1. Akira Funahashi, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano, The Impact of Output Selection Function on Adaptive Routing, ISCA Information: An International Journal, Vol 4, No.4, pp. 541-550, 2001
  2. Tsuyoshi Abe, Tomohiro Morimura, Takayuki Suzuki, Kensuke Tanaka, Michihiro Koibuchi, Keisuke Iwai, Hideharu Amano ASCA chip set: Key components of multiprocessor architecture for multi-grain parallel processing, An international Symposium on Low-Power and High-Speed Chips COOL Chips, Apr. 2001
  3. Michihiro Koibuchi, Akiya Jouraku, Akira Funahashi, Hideharu Amano, MMLRU selection function: An Output Selection Function on Adaptive Routing ISCA 14th International Conference on Parallel and Distributed Computing Systems(PDCS-2001), pp.1-6, Aug. 2001
  4. Michihiro Koibuchi, Akira Funahashi, Akiya Jouraku, Hideharu Amano, L-turn routing: An Adaptive Routing in Irregular Networks(In Japanese) IPSJ Journal of High Performance Computing System, Vol.42 No.SIG 9(HPS3),pp.119-134, Aug. 2001
  5. Michihiro Koibuchi, Akira Funahashi, Akiya Jouraku, Hideharu Amano, The Impact of Output Selection Function on Adaptive Routing(In Japanese) IPSJ Journal, Vol.42, No.4, pp.704-713, Apr. 2001
  6. Michihiro Koibuchi, Akira Funahashi, Akiya Jouraku, Hideharu Amano, L-turn Routing: An Adaptive Routing in Irregular Networks, the International Conference on Parallel Processing(ICPP'01), pp.374-383,Sep. 2001
  7. Akiya Jouraku, Michihiro Koibuchi, Akira Funahashi, Hideharu Amano, Routing Algorithms on 2D Turn Model for Irregular Networks, the Sixth International Symposium on Parallel Architectures, Algorithms, and Networks(I-SPAN'02), pp.289-294(invited paper), May. 2002
  8. Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano, The Impact of Path Selection Algorithm of Adaptive Routing for Implementing Deterministic Routing, The 2002 International Conference on Parallel and Distributed Processing Techniques and Applications(PDPTA'02), pp.1431-1437, Jun. 2002
  9. Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano, Deterministic Routing Techniques by Dividing into Sub-Networks in Irregular Networks, The IASTED International Conference on Networks, Parallel and Distributed Processing, and Applications (NPDPA 2002), pp.143-148, Oct. 2002
  10. Michihiro Koibuchi, Akiya Jouraku, Konosuke Watanabe, Hideharu Amano, Descending Layers Routing: A Deadlock-Free Deterministic Routing using Virtual Channels in System Area Networks with Irregular Topologies, the International Conference on Parallel Processing(ICPP'03), pp.537-536, Oct. 2003
  11. Michihiro Koibuchi, Konosuke Watanabe, Kenichi Kono, Akiya Jouraku, Hideharu Amano, Performance Evaluation of Routing Algorithms in RHiNET-2 Cluster, IEEE International Conference on Cluster Computing (Cluster2003), pp.395-402, Dec. 2003
  12. Kenichiro Anjo, Yutaka Yamada, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano, BLACK-BUS: A New Data-Transfer Technique using Local Address on Networks-on-Chips, 18th International Parallel and Distributed Processing Symposium (IPDPS), pp.10-17. Apr, 2004
  13. Yutaka Yamada, Hideharu Amano, Michihiro Koibuchi, Akiya Jouraku, Kenichiro Anjo, Katsunobu Nishimura Folded Fat H-Tree: an interconnection topology for Dynamic Reconfigurable Processor Array, The International Conference on Embedded And Ubiquitous Computing (EUC04),pp.301-311, Aug 2004 (Lecture Notes in Computer Science 3207)
  14. Michihiro Koibuchi, Juan C. Martinez, Jose Flich, Antonio Robles, Pedro Lopez, Jose Duato, Enforcing In-Order Packet Delivery in PC Clusters using Adaptive Routing, Workshop on High Performance Computing and Networking, pp.78-81, Nov 2004
  15. Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano, Path Selection Algorithm: The Strategy for Designing Deterministic Routing from Alternative Paths, PARALLEL COMPUTING, Volume 31, Issue 1, pp.117--130, Jan. 2005
  16. Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano, MMLRU Selection Function: A Simple and Efficient Output Selection Function in Adaptive Routing, IEICE Transactions on Information and Systems VOL.E88-D No.1, pp.109-118, Jan. 2005
  17. Juan Martnez, Jose Flich, Antonio Robles,Pedro Lopez, Jose Duato, Michihiro Koibuchi, In-Order Packet Delivery in Interconnection Networks using Adaptive Routing 19th International Parallel and Distributed Processing Symposium (IPDPS), Apr. 2005
  18. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips, The 2005 International Conference on Parallel and Distributed Processing Techniques and Applications(PDPTA'05), pp.1343--1349, Jun. 2005
  19. Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano, Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips, The 2nd International Workshop on Embedded Computing (ICPP Workshop) pp.273--280, Jun. 2005
  20. Tomohiro Otsuka, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano, VLAN-based Minimal Paths in PC Cluster with Ethernet on Mesh and Torus, the International Conference on Parallel Processing(ICPP'05), pp.567--576,Jun. 2005
  21. Michihiro Koibuchi, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano, Performance Evaluation of Deterministic Routings, Multicasts, and Topologies on RHiNET-2 Cluster, IEEE Transactions on Parallel and Distributed Systems, vol.16, no.8, pp.747--759, Aug. 2005
  22. Michihiro Koibuchi, Juan C. Martinez, Jose Flich, Antonio Robles, Pedro Lopez, Jose Duato, Enforcing In-Order Packet Delivery in System Area Networks with Adaptive Routing, Journal of Parallel and Distributed Computing(JPDC), pp.1223-1236, VOL 65 , Issue 10 Oct. 2005
  23. Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Hideharu Amano, Michihiro Koibuchi, A Parametric Study of Scalable Interconnects on FPGAs, The 2006 International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'06), pp.130-135, Jun 2006
  24. Tomohiro Otsuka, Michihiro Koibuchi, Tomohiro Kudoh, Hideharu Amano, A Switch-tagged VLAN Routing Methodology for PC Clusters with Ethernet, the International Conference on Parallel Processing(ICPP'06), pp.479-486, Aug 2006
  25. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano,``A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks'', ISCA International Conference on Parallel and Distributed Computing Systems (PDCS-2006), pp.24-31, Sep 2006
  26. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, ``Enforcing Dimension-Order Routing in On-Chip Torus Networks without Virtual Channels'', The 2006 International Symposium on Parallel and Distributed Processing and Applications (ISPA-06), pp.207-218, Dec 2006
  27. Michihiro Koibuchi, Tsutomu Yoshinaga, Yasuhiko Nishimura, A Partial Irregular-Network Routing on Faulty k-ary n-cubes, International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA) pp.57-64, 2006
  28. Tsutomu Yoshinaga, Shojirou Kamakura,Michihiro Koibuchi, Predictive Switching in 2D Torus Routers'', International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA), pp.65-72, 2006
  29. Michihiro Koibuchi, Kenichiro Anjo, Yutaka Yamada,Akiya Jouraku, Hideharu Amano, A Simple Data Transfer Technique using Local Address for Networks-on-Chips, IEEE Transactions on Parallel and Distributed Systems, Vol.17, No. 12, pp. 1425-1437, Dec 2006
  30. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network, 21st International Parallel and Distributed Processing Symposium (IPDPS), pp.80(the full paper(10page) is stored in its CD-ROM.), Mar 2007
  31. Akiya Jouraku, Michihiro Koibuchi, Hideharu Amano, An Effective Design of Deadlock-Free Routing Algorithms Based on 2-D Turn Model for Irregular Networks, IEEE Transactions on Parallel and Distributed Systems, Vol.18, No.3, pp.320-333, Mar. 2007
  32. Shigeo Urushidani, Shunji Abe, Kensuke Fukuda, Jun Matsukata, Yusheng Ji, Michihiro Koibuchi, Shigeki Yamada, Architectural Design of Next-generation Science Information Network, IEICE Transactions on Communications, VOL.E90-B No.5, pp.1061-1070, May 2007
  33. Jumpot Phuritatkul, Kien Nguyen, Michihiro Koibuchi, Yusheng Ji, Kensuke Fukuda, Abe Shunji, Jun Matsukata, Shigeo Urushidani, and Shigeki Yamada, ``Investigating the QoS Performance on a Testbed Network'', International Workshop on Performance Modeling and Evaluation in Computer and Telecommunication Networks (PMECT07), pp.1267-1272, Aug 2007
  34. Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, ``A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems'',The International Conference on Field Programmable Logica and Applications (FPL), pp.383-388, Aug 2007
  35. Shigeru Urushidani, Jun Matsukata, Yusheng Ji, Shuji Abe, Kensuke Fukuda, Michihiro Koibuchi, Shigeki Yamada, ``Layer-1 Bandwidth on Demand Services in SINET3'', IEEE Globecom 2007 Optical Networks and Systems Symposium, pp.26-30, Nov 2007
  36. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, ``Tightly-Coupled Multi-Layer Topologies for 3-D NoCs'', pp.75 (the full paper(10page) is stored in its CD-ROM.), Sep 2007
  37. Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano, ``Performance Improvement Methodology for ClearSpeed's CSX600'', the International Conference on Parallel Processing(ICPP'07),Sep 2007
  38. Shigeru Urushidani, Jun Matsukata, Kensuke Fukuda, Yusheng Ji, Shuji Abe, Michihiro Koibuchi, Shigeki Yamada, ``Implementation of Multilayer VPN Capabilities in SINET3'', the 33rd European Conference and Exhibition on Optical Communication (ECOC 2007), vol 3, pp. 103-103, Sep 2007
  39. Hiroki Matsutani, Michihiro Koibuchi, D. Frank Hsu, Hideharu Amano, "Three-Dimensional Layout of On-Chip Tree-Based Networks", The 9th International Symposium on Parallel Architectures, Algorithms and Networks (I-SPAN), pp.281-288, May, 2008
  40. Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, ``A Port Combination Methodology for Application-Specific Networks-on-chip on FPGAs'', IEICE Transactions on Information and Systems (Special Section on Reconfigurable Systems), Vol.E90-D No.12, pp.1914-1922, Dec 2007
  41. Tsutomu Yoshinaga, Hirokazu Murakami, Michihiro Koibuchi, ``Impact of Predictive Switching in 2-D Torus Networks'', International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA), pp.11-19, Dec 2007
  42. Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano, "Run-Time Power Gating of On-Chip Routers Using Look-Ahead Routing", The 13th Asia and South Pacific Design Automation Conference (ASP-DAC), pp.55-60, Jan 2008
  43. Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano, ``Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks'', Proc. of the 2nd ACM/IEEE International Symposium on Networks-on-Chip (NOCS'08), pp.23-32, Apr 2008
  44. Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy M. Pinkston, ``A Lightweight Fault-tolerant Mechanism for Network-on-chip'', Proc. of the 2nd ACM/IEEE International Symposium on Networks-on-Chip (NOCS'08), pp.13-22, Apr 2008
  45. Shigeo Urushidani, Yusheng Ji, Jun Matsukata, Kensuke Fukuda, Shunji Abe, Michihiro Koibuchi, Shigeki Yamada, ``Implementation of QoS Control Capabilities in SINET3'', 4th International Telecommunication Networking Workshop on QoS in Multiservice IP Networks (IT-NEWS2008), pp. 40-45, Feb 2008.
  46. Shigeo Urushidani, Kensuke Fukuda, Yusheng Ji, Shunji Abe, Michihiro Koibuchi, Motonori Nakamura, Shigeki Yamada, Kaori Shimizu, Rie Hayashi, Ichiro Inoue, and Kohei Shiomoto, ``Resource Allocation and Provision for Bandwidth/Networks on Demand in SINET3'', 2008 2nd IEEE International Workshop on Bandwidth on Demand (BoD) Apr, 2008
  47. Koichi Inoue, Dai Akashi, Michihiro Koibuchi, Hideyuk i Kawashima, Hiroaki Nishi, ``Semantic router using data stream to enrich services'', International Conference on Future Internet Technologies (CFI08), pp.20-23, June 2008
  48. Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, ``A Link Removal Methodology for Network-on-Chip on Reconfigurable Systems'', Proc. of the 18th International Conference on Field Programmable Logic and Applications (FPL'08), pp.269-274, Sep 2008
  49. Takafumi Watanabe, Masahiro Nakao, Tomoyuki Hiroyasu, Tomohiro Otsuka, Michihiro Koibuchi, ``The Impact of Topoloy and Link Aggregation on PC Cluster with Ethernet'',(Work-in-progress presentation) IEEE International Conference on Cluster Computing (Cluster2008), pp.380-385, Sep. 2008
  50. Hiroki Matsutani, Michihiro Koibuchi, and Hideharu Amano, Tsutomu Yoshinaga, ``Prediction Router: Yet Another Low Latency On-Chip Router Architecture'', The 15th International Symposium on High-Performance Computer Architecture (HPCA), pp.367-378, Feb. 2009
  51. Michihiro Koibuchi, ``A Partially Network Reconfiguration Mechanism on Two-dimensional Mesh and Torus with Faults'', The IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN), pp.91-96, Feb 2009
  52. Jumpot Phuritatkul, Kien Nguyen, Michihiro Koibuchi, Yusheng Ji, Kensuke Fukuda, Shunji Abe, Jun Matsukata, Shigeo Urushidani, Shigeki Yamada, ``Impact of QoS Operations on an Experimental Testbed Network'', Simulation Modelling Practice and Theory, Vol. 17, Issue 3, pp. 528-537, Wiley InterScience (2009)
  53. Shigeo Urushidani et al (Michihiro Koibuchi is 5th author, 11 authors in total), ``Design of Versatile Academic Infrastructure for Multilyaer Network Services'', IEEE Journal on Selected Areas in Communications (JSAC) Vol. 27, Issue. 3, 253-267, Apr 2009
  54. Yuto Hirata, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, ``Low-Power Variable-Pipeline Router using Pipeline-Stage Integration'', Proc. of the 12th IEEE International Symposium on Low-Power and High-Speed Chips (COOL Chips XII), Poster session, p.155, Apr 2009
  55. Michihiro Koibuchi, Hiroki Matsutani, "Chapter 3: Networks-on-Chip Protocols" in "Networks-on-Chips: Theory and Practice", Edited by Fayez Gebali, Haytham Elmiligi, Mohamed Watheq El-Kharashi, CRC Press, Mar 2009. ISBN-10: 1420079786
  56. Michihiro Koibuchi, Tomohiro Otsuka, Hiroki Matsutani, Hideharu Amano, ``An On/Off Link Activation Method for Low-Power Ethernet in PC Clusters'', 22nd International Parallel and Distributed Processing Symposium (IPDPS), CD-ROM, May 2009
  57. Jose Miguel Montanana, Michihiro Koibuchi, Takafumi Watanabe, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano, ``An On/Off Link Activation Method for Power Regulation in InfiniBand'', Proc. of the 2009 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'09), , pp. 289-295, Jun 2009
  58. Shigeo Urushidani, Kensuke Fukuda, Yusheng Ji, Michihiro Koibuchi, Shunji Abe, Motonori Nakamura, Shigeki Yamada, Kaori Shimizu, Rie Hayashi, Ichiro Inoue, Kohei Shiomoto, and Hiroyuki Tanuma, ``Implementation and Evaluation of Layer-1 Bandwidth-on-Demand Capabilities in SINET3,'' accepted by IEEE International Conference on Communications (ICC 2009)
  59. Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, and Hideharu Amano, ``Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network'', IEEE Transactions on Parallel and Distributed Systems, Vol. 20, No. 8, pp. 1126-1141, Aug 2009
  60. Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Akihiro Shitara, Kenichi Miura, Hideharu Amano, ``Performance Analysis of ClearSpeed's CSX600 Interconnects'', IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA), 203-210, Aug 2009
  61. Jose Miguel Montanana, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, ``Balanced Dimension-Order Routing for k-ary n-cubes'', Proc. of the 4th International Symposium on Embedded Multicore Systems-on-Chip (MCSoC'09), Sep 2009 (CD-ROM)
  62. Tomoyuki Hiroyasu, Kozo Kawasaki, Michihiro Koibuchi, Shigeo Urushidani, Mitsunori Miki and Masato Yoshimi, Efficient Scheduling Algorithms on Bandwidth Reservation Service of Internet using Genetic Algorithm, The 9th International Conference on Intelligent Systems Design and Applications (ISDA), pp.683-688, Dec 2009
  63. Sen In, Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, and Hideharu Amano ``Performance, Cost, and Power Evaluations of On-Chip Network Topologies in FPGAs'', The IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN), pp.181-189, Feb 2010
  64. Yu Kojima, Hiroki Matsutani, Michihiro Koibuchi, and Hideharu Amano ``A low-power fault-tolerant NoC using error correction and detection codes'', The IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN), pp.111-118, Feb 2010
  65. Shigeo Urushidani, Kensuke Fukuda, Yusheng Ji, Shunji Abe, Michihiro Koibuchi, Motonori Nakamura, Shigeki Yamada, Michihiro Aoki, ``Expansion of Bandwidth-on-Demand Capabilities in Japanese Academic Backbone Network'', IEEE BoD 2010
  66. Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyo shi Usami, Hiroshi Nakamura, Hideharu Amano, ``Ultra Fine-Grained Run-Time Power Gating of On-Chip Routers for CMPs'', Proc. of the 4th ACM/IEEE International Symposium on Networks-on-Chip (NOCS'10), pp.61-68, May 2010
  67. Jose Miguel Montanana, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, ``Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks'', The 5th IEEE International Conference on Networking, Architecture, and Storage (NAS 2010), pp.218-227, July 2010
  68. Yuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, ``A Deadlock-free Non-minimal Fully Adaptive Routing using Virtual Cut-through Switching'', The 5th IEEE International Conference on Networking, Architecture, and Storage (NAS 2010), pp.431-438, July 2010
  69. Tomoaki Makino, Michihiro Koibuchi, Hideyuki Kawashima, Koichi Inoue, Hiroaki Nishi, ``Hardware Architecture for Supporting High-speed Database Insertion on Service-oriented Router for Future Internet'', Proc. of the 2010 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'10), pp. XX, Jun 2010
  70. Yasutsugu Nagatomi, Michihiro Koibuchi, Hideyuki Kawashima, Ko ichi Inoue and Hiroaki Nishi, A Regular Expression Processor embedded in Service-friendly Router for Future Internet 5th International Symposium on Embedded Multicore Systems-on-chip (MCSoC,2010,Se p. 13)
  71. Yuto Hirata, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, ``A Variable-pipeline On-chip Router Optimized to Traffic Pattern'', Proc. of the 3rd International Workshop on Network on Chip Architectures (NoCArc'10), pp.57-62, Dec 2010
  72. Cisse Ahmadou Dit ADI, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutumo Yoshinaga, ``An Efficient Path Setup for a Hybrid Photonic Network-on-Chip'', Proc. of the 2nd Workshop on Ultra Performance and Dependable Acceleration Systems (UPDAS'10), pp.156-161, Nov 2010
  73. Michihiro Koibuchi, Tomohiro Otsuka, Tomohiro Kudoh, Hideharu Amano, ``A Switch-tagged Routing Methodology for PC Clusters with VLAN Ethernet'', IEEE Transactions on Parallel and Distributed Systems, Vol.22, No.2, pp.217-230, Feb 2011
  74. Yuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, ``Semi-deflection Routing: A Non-minimal Fully-adaptive Routing for Virtual Cut-through Switching Network'', International Journal of Computer and Network Security (IJCNS), Vol.2, No.10, pp.52-58, Oct 2010.
  75. Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano,``An Analytical Network Performance Model for SIMD Processor CSX600 Interconnects, Journal of Systems Architecture, Vol.57 Issue 1, January, 2011
  76. Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano, ``Performance, Area, and Power Evaluations of Ultra Fine-Grained Run-Time Power-Gating Routers for CMPs'', IEEE Transactions on Computer-Aided Design of Integrated Circuits (TCAD), Vol.30, No.4, pp.520-533. Apr 2011
  77. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga, ``Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors'', IEEE Transactions on Computers, Vol.60, No.6, pp.783-799, Jun 2011
  78. Hiroki Matsutani, Yasuhiro Take, Daisuke Sasaki, Masayuki Kimura, Yuki Ono, Yukinori Nishiyama, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano, ``A Vertical Bubble Flow Network using Inductive-Coupling for 3-D CMPs'', Proc. of the 5th ACM/IEEE International Symposium on Networks-on-Chip (NOCS'11), pp.49-56, May 2011
  79. Cisse Ahmadou Dit ADI, Hiroki Matsutani, Michihiro Koibuchi, \ Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga pp. 244-259, The International Journal of Networking and Computing,Vol.1, Num.2, July 2011
  80. Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano, ``A Dynamic Link-Width Optimization for Network-on-Chip'', Proc. of the 1st International Workshop on Cyber-Physical Systems, Networks, and Applications (CPSNA'11), Poster session, pp.106-108, Aug 2011
  81. Michihiro Koibuchi, Takafumi Watanabe, Atsushi Minamihata, Masahiro Nakao,Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano, Performance Evaluation of Power-aware Multi-tree Ethernet for HPC Interconnects, The Second International Conference on Networking and Computing, pp.50-57, Dec, 2011(best paper award)
  82. Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano, ``A Multi-Vdd Dynamic Variable-Pipeline On-Chip Router for CMPs'', Proc. of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC'12), pp.407-412, Jan. 2012 (best paper candidate)
  83. Kensuke Fukuda, Michihiro Aoki, Shunji Abe,Yuseng Ji, Michihiro Koibuchi, Motonori Nakamura, Shigeki Yamada, Shigeo Urushidani, ``Impact of Tohoku Earthquake on R&E Network in Japan'', Proc of ACM CoNEXT Special Workshop on the Internet and Disasters (WoID), Dec 2011
  84. J. Flich, T. Skeie, A.Mejia, O. Lysne, P. Lopez, A. Robles, J. Duato, M. Koibuchi, T. Rokicki, and J. C. Sancho, ``A Survey and Evaluation of Topology Agnostic Routing Algorithms'', IEEE Transactions on Parallel and Distributed Systems, Vol.23, No.3, pp.405-425, Mar. 2012
  85. Michihiro Koibuchi, Shin-ichi Ishida, Hiroaki Nishi, The Impact of Routing Cache on High-Performance Switches, The 10th International Conference on Optical Internet (COIN2012), Tuj2,May 2012
  86. Shin-ichi Ishida, Michihiro Koibuchi, Hiroaki Nishi, ``A Case for Routing Cache on HPC Switches'' IEICE Communications Express, Vol. 1 (2012) No. 1 pp. 49-53
  87. Shigeo Urushidani, Michihiro Aoki, Kensuke Fukuda, Shunji Abe, Motonori Nakamura, Michihiro Koibuchi, Yusheng Ji, and Shi geki Yamada, ``Highly available network design and resource management of SINET4,'' accepted for publication on Telecommunication Systems Journal (2012)
  88. Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova, ``A Case for Random Shortcut Topologies for HPC Interconnects'', The 39th International Symposium on Computer Architecture (ISCA), pp.177-188, June 2012
  89. Takeo Nakamura, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano, ``Fine-Grained Power Control Using A Multi-Voltage Variable Pipeline Router'' Prof. of 6th IEEE International Symposium on Embedded Multicore Systems-on-chip (MCSoC), Sep 2012, 6 pages
  90. Yicheng Guan, Cisse Ahwadou Dit Adi, Takefumi Miyoshi, Michihiro Koibuchi, Hidetsugu Irie, Tsutomu Yoshinaga, ``Throttling Control for Bufferless Routing in On-Chip Networks'', Prof. of 6th IEEE International Symposium on Embedded Multicore Systems-on-chip (MCSoC), Sep 2012, 6 pages
  91. Ikki Fujiwara, Michihiro Koibuchi, Henri Casanova, ``Cabinet Layout Optimization of Supercomputer Topologies for Shorter Cable Length'', The International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT), pp.227-232, Dec 2012
  92. Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Yasuhiro Take, Daisuke Sasaki, Hao Zhang, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano, ``A Case for Wireless 3D NoCs for CMPs'', Proc. of the 18th Asia and South Pacific Design Automation Conference (ASP-DAC'13), pp.23-28, Jan 2013. (Best Paper Award)
  93. Michihiro Koibuchi, Ikki Fujiwara, Hiroki Matsutani, Henri Casanova, Layout-conscious Random Topologies for HPC Off-chip Interconnects, The 19th International Symposium on High-Performance Computer Architecture (HPCA), pp.484-495, Feb. 2013
  94. Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Hidehar u Amano ``Headfirst Sliding Routing: A Time-Based Routing Scheme for Bus-NoC Hybrid 3-D Architecture'', Proc. of the 7th ACM/IEEE International Symposium on Networks-on-Chip (NOCS'13), pp.29-36, Apr 2013
  95. Yasuhiro Take, Hiroki Matsutani, Daisuke Sasaki, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano, ``3-D NoC with Inductive-Coupling Links for Building-Block SiPs'', IEEE Transactions on Computers (TC), vol.63, issue 3, pp.748-763, 2014, DOI:10.1109/TC.2012.249
  96. Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Dynamic Power On/Off Method for 3D NoCs with Wireless Inductive-Coupling Links, Proc. of the IEEE International Symposium on Low-Power and High-Speed Chips (COOL Chips XVI), pp.1-3, Apr 2013
  97. Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Performance Degradation by Deactivated Cores in 2-D Mesh NoCs, Prof. of 7th IEEE International Symposium on Embedded Multicore Systems-on-chip (MCSoC), pp.25-30, Sep 2013
  98. Van K. Nguyen, Nhat T. X. Le, Ikki Fujiwara, Michihiro Koibuchi, Distributed Shortcut Networks: Layout-aware Low-degree Topologies Exploiting Small-world Effect, the International Conference on Parallel Processing(ICPP), pp.572-581, Oct 2013
  99. Sarat Yoowattana, Ikki Fujiwara, Michihiro Koibuchi, Investigating Performance Advantages of Random Topologies on Network-on-Chip,The 18th Workshop on Synthesis And System Integration of Mixed Information technologies, Oct 2013
  100. Ahmed Shalaby, Mohammed Ragab, Victor Goulart, Ikki Fujiwara and Michihiro Koibuchi, Hierarchical Network Coding for Collective Communication on HPC Interconnects, the 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP 2014), Feb 2014
  101. Hiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu, Hideharu Amano, ``Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips'', Proc. of the 17th Design, Automation, and Test in Europe Conference (DATE'14), pp.1-6, Mar 2014
  102. Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova, Skywalk: a Topology for HPC Networks with Low-delay Switches, The 28th IEEE International Parallel & Distributed Processing Symposium (IPDPS 2014) 263-272, May 2014
  103. Swap-and-randomize: A Method for Building Low-latency HPC Interconnects Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova IEEE Transactions on Parallel and Distributed Systems (to be published)
  104. Extreme Big Data (EBD): Next Generation Big Data Infrastructure Technologies Towards Yottabyte/Year Satoshi Matsuoka, Hitoshi Sato, Osamu Tatebe, Michihiro Koibuchi, Ikki Fujiwara, Shuji Suzuki, Masanori Kakuta, Takashi Ishida, Yutaka Akiyama, Toyotaro Suzumura, Koji Ueno, Hiroki Kanezashi, Takemasa Miyoshi Supercomputing frontiers and innovations 1(2) 89-107, Oct 2014
  105. Fabien Chaix, Ikki Fujiwara, Michihiro Koibuchi, Darkfiber Planning for Extensible HPC Network Design Under Uncertainties, The 2nd International Symposium on Computing and Networking (CANDAR '14)
  106. Nguyen T. Truong, Van K. Nguyen, Nhat T. X. Le, Ikki Fujiwara, Fabian Chaix, Michihiro Koibuchi, Layout-aware Expandable Low-degree Topology, The 20th IEEE International Conference on Parallel and Distributed Systems (ICPADS 2014), pp.462--470, Dec. 2014
  107. Ikki Fujiwara, Michihiro Koibuchi, Tomoya Ozaki, Hiroki Matsutani, Henri Casanova, Augmenting Low-latency HPC Network with Free-space Optical Links, The 21st IEEE International Symposium on High Performance Computer Architecture (HPCA 2015) pp.390-401
  108. Ryuta Kawano, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, Optimized Core-links for Low-latency NoCs, The 23rd Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP 2015), pp.172-176, Mar 2015
  109. Ahmed Shalaby, Ikki Fujiwara, Michihiro Koibuchi, The Case for Network Coding for Collective Communication on HPC Interconnection Networks, IEICE Transactions on Information and Systems E98-D(3) 661-670, March 2015
  110. Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano,Tadao Naka mura, On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconn ect Bottleneck, Proc. of the ACM/IEEE International Symposium on Networks-on-Chip (NOCS), 2015 (t o appear)
  111. Seiichi Tade, Hiroki Matsutani, Michihiro Koibuchi and Hideharu Amano, A Metamorphotic Network-on-Chip for Various Types of Parallel Applications, the 26th IEEE International Conference on Application-specific Systems, Architectu res and Processors (ASAP) (to appear), July 2015
  112. Takahiro Kagami,Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda,Hideharu Amano, ``Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces'', IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (to appear)
  113. Y.Hu,H.Hara,I.Fujiwara,H.Matsutani,H.Amano,M.Koibuchi, ``Towards Tightly-coupled Datacenter with Free-space Optical Links,'', Int. Conf. on Cloud and Big Data Computing(ICCBDC) 2017, (to appear)

    (Correction)

    The wrong grant number was described in the Acknowledgement. We have corrected it as follows. Here
  1. Book Chapter
  2. Hiroki Matsutani, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano, "Chapter 10: 3-D NoC on Inductive Wireless Interconnect", Book of "3D Integration for NoC-based SoC Architectures" edited by Abbas Sheibanyrad, Frederic Petrot, Axel Janstch, pp.225-248, Springer, Dec 2010
  3. Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, Hideharu Amano, "Chapter 2: Run-Time Power-Gating Techniques for Low-Power On-Chip Networks", Book of "Low Power Networks-on-Chip" edited by Cristina Silvano, Marcello Lajolo, Gianluca Palermo, pp.21-44, Springer, Oct 2010
  4. Michihiro Koibuchi, Hiroki Matsutani, "Chapter 3: Networks-on-Chip Protocols", Book of "Networks-on-Chips: Theory and Practice" edited by Fayez Gebali, Haytham Elmiligi, Mohamed Watheq El-Kharashi, pp.65-94, CRC Press, Mar 2009

Patents

Two patents have been submitted (Japan, No.2007-123980, No.2007-135940) May 2007.

Awards

  1. IEEE Computer Society Japan Chapter Young Author Award 2007
  2. Best Paper Award, International Conference on Networking and Computing(ICNC), 2011
  3. Best Paper Candidate, Asia and South Pacific Design Automation Conference (ASP-DAC'12)
  4. Young Engineering Award, The 10th International Conference on Optical Internet (COIN2012) May 29 - 31, 2012
  5. Best Paper Award, Asia and South Pacific Design Automation Conference (ASP-DAC'13), Jan 2013

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