1.

Kenji Mizutani, Hiroshi Yamaguchi, Yutaka Urino and Michihiro Koibuchi, “Accelerating Parallel Data Processing Using Optically Tightly Coupled FPGAs", Journal of Optical Communications and Networking (JOCN), IEEE/OPTICA, Vol.14, Issue 2, pp.A166-A179 (2022)

2.

Kenji Mizutani, Hiroshi Yamaguchi, Yutaka Urino and Michihiro Koibuchi, “OPTWEB: A Lightweight Fully Connected Inter-FPGA Network for Efficient Collectives", IEEE Transactions on Computers (TC). Vol. 70 , Issue 6, pp.849-862, Jun. 2021

3.

Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano, “Designing High-Performance Interconnection Networks with Host-Switch Graphs", IEEE Transactions on Parallel and Distributed Systems, vol. 30, no. 2, pp. 315-330, Feb 2019

4.

Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura, “ Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers", IEEE Transactions on Computers (TC), Vol.66, No.4 pp.702-716, 2017

5.

Nguyen T. Truong, Ikki Fujiwara, Michihiro Koibuchi, Khanh-Van Nguyen, “Distributed Shortcut Networks: Low-latency Low-degree Non-random Topologies Targeting the Diameter & Cable Length Tradeoff", IEEE Transactions on Parallel and Distributed Systems, pp.989-1001, Vol. 28, Issue. 4, 2017

6.

Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano, “Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.24, No.2, pp.493-506, Feb 2016

7.

Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova, “Swap-and-randomize: A Method for Building Low-latency HPC Interconnects", IEEE Transactions on Parallel and Distributed Systems, pp.2051-2060, Vol. 26, Issue 7, Jul 2015

8.

J. Flich, T. Skeie, A.Mejia, O. Lysne, P. Lopez, A. Robles, J. Duato, M. Koibuchi, T. Rokicki, and J. C. Sancho, “A Survey and Evaluation of Topology Agnostic Routing Algorithms", IEEE Transactions on Parallel and Distributed Systems, Vol.23, No.3, pp.405-425, Mar 2012

9.

Michihiro Koibuchi, Tomohiro Otsuka, Tomohiro Kudoh, Hideharu Amano, “A Switch-tagged Routing Methodology for PC Clusters with VLAN Ethernet", IEEE Transactions on Parallel and Distributed Systems, Vol.22, No.2, pp.217-230, Feb 2011

10.

Michihiro Koibuchi, Kenichiro Anjo, Yutaka Yamada,Akiya Jouraku, Hideharu Amano, “A Simple Data Transfer Technique using Local Address for Networks-on-Chips", IEEE Transactions on Parallel and Distributed Systems, Vol.17, No. 12, pp. 1425-1437, Dec 2006

11.

Kien Trung Pham, Truong Thao Nguyen, Hiroshi Yamaguchi, Yutaka Urino, Michihiro Koibuchi, “Scalable Low-Latency Inter-FPGA Networks, Scalable Low-Latency Inter-FPGA Networks", IEEE International Parallel & Distributed Processing Symposium (IPDPS), pp.234-245, May 2022

12.

Michihiro Koibuchi, Ikki Fujiwara, Naoya Niwa, Tomohiro Totoki, Shoichi Hirasawa, “The Case forWaterImmersion Computer Boards", International Conference on Parallel Processing (ICPP), 29(10pages), Aug 2019

13.

Michihiro Koibuchi, Lambert Leong, Tomohiro Totoki, Naoya Niwa, Hiroki Matsutani, Hideharu Amano, Henri Casanova, “Sparse 3-D NoCs with Inductive Coupling, The 56th Design Automation Conference (DAC)", 49 (6pages), Jun 2019

14.

Michihiro Koibuchi, Tomohiro Totoki, Hiroki Matsutani, Hideharu Amano, Fabien Chaix, Ikki Fujiwara, Henri Casanova, “A Case for Uni-Directional Network Topologies in Large-Scale Clusters", The 19th IEEE International Conference on Cluster Computing (Cluster), pp.178-187, Sep 2017.

15.

Daichi Fujiki, Kiyo Ishii, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Henri Casanova, Michihiro Koibuchi, “High-Bandwidth Low-Latency Approximate Interconnection Networks",The International Symposium on High-Performance Computer Architecture(HPCA), pp.469 - 480, Feb 2017

16.

Koji Nakano, Daisuke Takafuji, Satoshi Fujita, Hiroki Matsutani, Ikki Fujiwara, Michihiro Koibuchi, “Randomly Optimized Grid Graph Under Geometric Constraints for Interconnection Networks", The International Conference on Parallel Processing(ICPP), pp.340-349, Aug 2016

17.

Ikki Fujiwara, Michihiro Koibuchi. Tomoya Ozaki, Hiroki Matsutani, Henri Casanova, “Augmenting Lowlatency HPC Network with Free-space Optical Links", The 21st IEEE International Symposium on High Performance Computer Architecture (HPCA), pp.390-401, Feb 2015

18.

Michihiro Koibuchi, Ikki Fujiwara, Hiroki Matsutani, Henri Casanova, “Layout-conscious Random Topologies for HPC Off-chip Interconnects", The 19th International Symposium on High-Performance Computer Architecture (HPCA), pp.484-495, Feb 2013

19.

Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova, “A Case for Random Shortcut Topologies for HPC Interconnects", The 39th International Symposium on Computer Architecture (ISCA), pp.177-188, Jun 2012, (SIGARCH Comput. Archit. News, vol.40, num.3, Jun 2012)

20.

Hiroki Matsutani, Michihiro Koibuchi, and Hideharu Amano, Tsutomu Yoshinaga, “Prediction Router: Yet Another Low Latency On-Chip Router Architecture", The 15th International Symposium on HighPerformance Computer Architecture (HPCA), pp.367-378, Feb 2009